1. Field of the Invention
The present invention relates to a circuit configuration of a pattern recognition apparatus for executing pattern recognition, detection of a specified object etc. by parallel operation of a neural network or the like.
2. Description of Related Art
Conventionally, the process of image recognition or voice recognition is divided into a type of executing in succession a recognition process algorithm specified for a certain object of recognition as a computer software, and a type of executing such algorithm by an exclusive parallel image processor (SIMD, MIMD machine etc.).
As for the latter, the Japanese Patent Application Laid-Open No. 6-6793 discloses an object recognition apparatus in which plural image processor units are employed to execute the process by DSP's provided in such processor units, and the obtained plural results are transferred to another unit for executing recognition of the object. For example an image is divided into plural areas which are processed in parallel respectively by the processor units, and the recognition of object is estimated in another processor unit by a neural network or fuzzy control.
Also for a hardware for executing hierarchical parallel processing by neural network, the Japanese Patent No. 2679730 discloses the architecture of a hierarchical neural network enabling to realize a multi-layered architecture by time-shared multiplex use of a single-layered hardware. It intends to realize multiple layers in equivalent manner by time-shared multiplex use of a single-layered hardware, and provides a neural network, formed by mutual connection of plural neuron models and comprising a single-layered unit assembly including plural neuron model units each of which is capable of generating a product of a time-shared multiplex analog signal with an external digital weighting data, integrating such product by time-shared addition through a capacitor and outputting a voltage through a non-linear output function in time-shared manner, a feedback unit for feeding the output of the aforementioned single-layered unit assembly back to the input unit thereof, and a control unit for executing control for time-shared multiplexing of the analog signals from the units constituting the aforementioned single-layered unit assembly and for time-shared multiplex use of the aforementioned single-layered unit assembly through the feedback unit, whereby the neural network of a hierarchical structure in equivalent manner is constructed by the time-shared multiplex use of the single-layered unit assembly.
Also the U.S. Pat. No. 5,892,962 discloses a processor as a hardware employing FPGA (field programming gate array). In such processor, each FPGA is provided with a memory for holding the result of processing in FPGA, and the processing is executed by reading the results in such memories.
Among such conventional technologies, the object recognition apparatus disclosed in the Japanese Patent Application Laid-Open No. 6-6793 is capable of processing in several stages for the areas assigned to the image processor units and for the further divided smaller areas back to the original areas, but is incapable of hierarchical processing by parallel process' with other plural processor units for the obtained plural process results. It is also not capable of reading the results of processing, nor capable of spatially integrating the results from the areas.
Also the hierarchical neural network disclosed in the Japanese Patent No. 2679730 is associated with a drawback that the types of the practically realizable processes are quite limited because of the absence of a unit for variably and arbitrarily controlling the interlayer coupling.
Also the FPGA-based processor disclosed in the U.S. Pat. No. 5,892,962 requires complex wirings in order to read out the intermediate results retained in the memories.